Systems often implement a collection of different interconnect interfaces for inter-device control and communication. Two popular interconnect interfaces include an interface established by the Joint Test Action Group (JTAG) referred to as the “JTAG interface”, and a de facto standard interface known as the Serial Peripheral Interface (SPI). The JTAG interface is incorporated into IEEE 1149.1, which is a standard defining boundary scan test logic for integrated circuits (ICs). While the JTAG and SPI interfaces generally have similar control and communication functionality, the interfaces themselves and the protocols used to transfer data are different.
It is often preferred that one master controller controls and communicates with the peripheral devices in a system. When the peripheral devices have different interfaces (e.g., JTAG, SPI, etc.), a bridge circuit can be employed to bridge control and communication from one kind of interface to another kind of interface. Prior implementations of bridges that translate between JTAG and SPI interfaces involve memory buffers for storing control tasks and data, and a sequencer state machine or microprocessor. With such bridges, control or communication transactions from one interface are buffered and handed to the bridge circuit, and the bridge circuit reconstructs the equivalent transaction for the other interface. Such bridges can require significant memory and logic resources, and can add significant latency between transactions, particularly round-trip transactions (e.g., request and response transactions).